The present invention relates to a dynamic memory device in which a plurality of pairs of bit lines are connected to a single sense amplifier.
The integration density of dynamic random access memory devices has been improved remarkably in recent years. The improvement of the integration density has depended largely on the improvement of lithography accuracy and reduction of a design rule resulting from the improvement of the working accuracy. Advances in circuit technology further contributed to the improvement of the integration density.
An example of the improved circuit technology is described by S. S. Eaton et al in their paper entitled "A 100 ns 64 Kilo Dynamic RAM using Redundancy techniques" in ISSCC Digest of Technical Papers, p 84, Feb. 1981. The paper describes the dynamic memory device of the shared sense amplifier system. That technique can improve an integration density by remarkably reducing the space of the peripheral circuitry associated with the dynamic circuit section. In the prior dynamic memory device, a pair of bit lines is connected to a single sense amplifier. For increasing the number of memory cells using the prior art technique, the number of memory cells connected to the pair of bit lines must be increased. When the number of the memory cells connected to a single bit line is increased, the stray capacitance of the bit line increases reducing the input signal to the sense amplifier in read/write mode. This is undesirable. When an amount of charge to be stored in a single memory cell is reduced to increase bit density, the input signal to the sense amplifier also decreases. In the prior art 64K bit memory device in which a pair of bit lines is connected to a single sense amplifier, 64 memory cells are connected to a single bit line. For this reason, it is difficult to connect 128 memory cells to a single bit line to form a memory device of 256K bits.
In the shared sense amplifier system, two pairs of bit lines are connected to a single amplifier, a switching transistor is connected between the sense amplifier and each bit line. For sensing or writing data from and to the cells, the switching transistor is driven to electrically connect one of the two pairs of the bit lines to the sense amplifier. This shared sense amplifier system will be called a multibit line system.
A useful feature of the multibit line system resides in that the input signal to the sense amplifier is not reduced even if the number of memory cells to be connected to a single sense amplifier are increased as compared with the prior art two bit line system. Accordingly, by connecting 64 memory cells to a single bit line, a dynamic RAM of 256K bits or more can be formed.
A disadvantage of the conventional multibit line system is that the write time of data into memory cells is longer than that of the two bit line type of the prior art dynamic memory device. In the prior two bit line system, a pair of bit lines connected to the sense amplifier is directly connected to a pair of the data bus lines. For this reason, date can be written into the memory cells at a relatively high speed. On the other hand, in the conventional multibit line system, ends of the first pair of the bit lines are connected to a sense amplifier through switching transistors. The other ends of the first pair of bit lines are directly connected to a pair of data lines through switching transistors. Therefore, the conventional multibit line system allows data to be written into the memory cells connected to this first pair of bit lines at a high speed. However, ends of the second pair of the bit lines are connectecd to the sense amplifier through switching transistors and the other ends thereof are extended in the opposite direction to that of the first pair of bit lines. When data is written into the memory cells connected to the second pair of bit lines, data must be written through the switching transistors inserted into the first and second pairs of bit lines. For this reason, it takes a relatively long time to write data.